1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) device, and more particularly to a fabricating method of an array substrate for the LCD device having polysilicon thin film transistor (TFT).
2. Description of the Related Art
In a conventional process for forming a polysilicon layer, an intrinsic amorphous silicon layer is formed on an insulating substrate by using a plasma chemical vapor deposition (PCVD) method or a low pressure chemical vapor deposition (LPCVD) method. When the amorphous silicon layer has a thickness of about 500 Å (angstrom), it is recrystallized into a polysilicon layer by a crystallization method. The crystallization method is generally one of the following: a laser annealing method, a solid phase crystallization (SPC) method, and a metal induced crystallization (MIC) method.
In the laser annealing method, an excimer laser beam is applied to the amorphous silicon layer on an insulating substrate to form a polysilicon layer. For the SPC method, a heat-treatment is applied to the amorphous silicon layer at a high temperature for a time period sufficient to form the polysilicon layer. For the MIC method, a metal layer is deposited on the amorphous silicon layer and the deposited metal layer is used as a crystallization seed. In case of the MIC method, a large sized glass substrate may be used as the insulating substrate.
The laser annealing method has recently become a more prevalent method in forming a polysilicon layer. The laser annealing method forms an amorphous silicon layer on the insulating substrate melting the amorphous silicon layer with a laser. Then, the melted amorphous silicon layer is cooled to form a polysilicon layer.
The SPC method forms a buffer layer on a quartz substrate that can withstand temperatures higher than 600° C. (degrees Celsius). The buffer layer prevents the quartz substrate from contaminating other regions. Next, an amorphous silicon layer is deposited on the buffer layer and is heated in a furnace to a sufficient temperature to form a polysilicon layer.
The MIC method deposits a catalytic metal layer on an amorphous silicon layer which is then heated to form a polysilicon layer. The amorphous silicon layer of the MIC method is crystallized more rapidly with the catalytic metal layer than the SPC method, and the process temperature of the MIC is lower than the SPC method.
Generally, in using the polysilicon as an active layer for a coplanar type TFT, a gate electrode is formed over the active layer upon an array substrate.
FIG. 1 is a schematic cross-sectional view of an array substrate having a conventional coplanar type thin film transistor for a liquid crystal display device.
In FIG 1, a coplanar type TFT includes a semiconductor layer 8 formed on a substrate 1. The semiconductor layer 8 has a first region (the active region 14) and a second region (the source and drain regions 16 and 17). A gate electrode 12 is formed over the active region 14 and a gate insulating layer 10 is interposed therebetween. An interlayer insulating layer 18, including contact holes 16a and 17a corresponding to the source and drain regions 16 and 17, is formed on the gate electrode 12. Then, source and drain electrodes 20 and 22 are formed on the interlayer insulating layer 18, and electrically connected to the source and drain regions 16 and 17 through the contact holes 16a and 17a, respectively. A transparent pixel electrode 28 is electrically connected to the drain electrode 22 and a passivation layer 26 is interposed therebetween.
As shown in FIG. 1, the driving characteristic of the TFT is directly related to the conductivity between the source and drain regions 16 and 17, and the source and drain electrodes 20 and 22, and the drain electrode 22 and the pixel electrode 28. With the interlayer insulating layer 18 and the passivation layer 26 etched for inter-contact, the conductivity properties depend on the interlayer insulating layer 18 and the passivation layer 26, respectively. During the etching process, several problems such as low etching rate or low etching uniformity may occur.
FIGS. 2A to 2C are schematic cross-sectional views showing the fabricating processes of an array substrate having a conventional coplanar type thin film transistor.
In FIG. 2A, a first insulating layer 2 and an amorphous silicon layer are subsequently formed on a substrate 1. After crystallizing the amorphous silicon layer by a specific method to form a polysilicon layer, the polysilicon layer is patterned to form a semiconductor layer 8 in the shape of island. The first insulating layer 2 is a buffer layer which prevents alkyl radicals from substrate 1 from diffusing to the semiconductor layer 8 at a high temperature.
In FIG. 2B, a second insulating layer 10 of silicon nitride (SiNx) or silicon oxide (SiO2) is formed on the semiconductor layer 8. The second insulating layer 10 is the gate insulating layer. The depositing and patterning of a conductive metallic material forms a gate layer 12 on the second insulating layer 10, at a region corresponding to an active region 14 of the semiconductor layer 8. The semiconductor layer 8 has first and second regions that form an intrinsic silicon region 14 and a doped silicon region 16 and 17, respectively. The second region 16 and 17 is located at the sides of the first region 14. The second insulating layer 10 and the gate layer 12 are formed over the first region 14 of the semiconductor layer 8. To reduce the number of masks, the second insulating layer 10 and the gate layer 12 are formed with same patterns.
After forming the gate layer 12, an ion doping process is performed on the second region 16 and 17 of the semiconductor layer 8 forming an ohmic contact layer. During the ion doping process, the gate layer 12 acts as an ion-stopper and prevents dopants from permeating into the first region 14 of the semiconductor layer 8.
In FIG. 2C, a third insulating layer 18, an interlayer insulating layer, is formed on the gate layer 12, the second region 16 and 17 of the semiconductor layer 8 and the second insulating layer 10. Next, the third insulating layer 18 is patterned to form the first and second contact holes 16a and 17a at a region corresponding to the second region 16 and 17. The third insulating layer 18 includes one of the inorganic material groups such as SiO2, SiNx, TEOS or Al2O3.
Source and drain electrodes 20 and 22 are formed for connection to the second region 16 and 17 of the semiconductor layer 8 through the first and second contact holes 16a and 17a, respectively.
As shown in FIG. 1, a passivation layer 26 is deposited on the entire surface of the substrate and patterned to form a third contact hole 17b to expose a portion of the drain electrode 22. Then, a transparent layer is deposited and patterned forming a pixel electrode 28 that is electrically connected to the exposed drain electrode 22 through the third contact hole 17b. 
The source and drain electrodes are connected to the impurity-doped polysilicon region through the first and second contact holes 16a and 17a formed by etching the interlayer insulating layer.
FIGS. 3 and 4 are schematic, magnified, cross-sectional views of “A” and “B” (of FIG. 1) formed by dry and wet etching methods of the interlayer insulating layer, respectively.
In FIG. 3, a photo resist (PR) is coated on the interlayer insulating layer 18 and then exposed with a mask (not shown) to form a PR pattern 30. After developing and stripping the PR, a portion of the interlayer insulating layer 18, corresponding to the second region 16 and 17 (of FIG. 2C) of the semiconductor layer, is exposed. Then, the exposed portion of the third insulating layer is etched by dry etching method to expose the second region 16 and 17, doped with n-or p-type impurities.
Since the etch rate of dry etching method is slow, the desired depth is limited. Furthermore, as the etch time increases, the PR pattern hardens and prevents the stripping away process. Therefore, with the dry etching method, the etching condition is controlled to remove the interlayer insulating layer before the PR pattern hardens. However, if the thickness of the interlayer insulating layer 18 is not uniform, a portion of the interlayer insulating layer 18 will remain so that the second region 16 and 17 is partially covered with the residual interlayer insulating layer “C”. Alternatively, if the second region is exposed to the plasma, the device characteristics deteriorate because the contact resistance between the source and drain electrodes and the second region increases. Therefore, process reliability and a shorter etch time are necessary for the dry etching method of the interlayer insulating layer. For the passivation layer 28 (of FIG. 1), the same phenomenon can occur.
In FIG. 4, the interlayer insulating layer 18 is etched by wet etching method. Although a better etching profile is acquired with wet etching, it takes longer than dry etching, and a critical dimension (CD) loss may occur due to the over-etch of the interlayer insulating layer 18 at a portion “D” contacting the PR 30. Furthermore, the driving characteristic of the LCD panel can be degraded and a point defect can occur if an electrical opening between the source and drain electrodes, and the second region occurs due to a PR residue.